## Daisy II: The ALU2 min read

#### Adders

A half adder adds two binary digits. A full adder adds three bits.

## Arithmetic logic unit

The chips built thus far have been generic, i.e. their designs are universal and would hold for any computer. The ALU is the first bit of proprietary chip added into the mix. There is no universal way of designing an ALU. It all depends on product requirements.

This ALU accepts two 16-bit inputs `x`

and `y`

, and six control bits and returns a 16-bit `output`

. The control bits are as follows (in order of their precedence):

`zx`

zero x-input`zy`

zero y-input`nx`

invert x-input`ny`

invert y-input`f`

function selector.`0`

for`x AND y`

,`1`

for`x + y`

.`no`

invert output

Additionally, the ALU computes two 1-bit outputs:

`zr`

: indicates whether the ouput is zero.`1`

if`output = 0`

,`0`

otherwise.`ng`

: indicates whether the output is negative.`1`

if`output < 0`

,`0`

otherwise.

Theoretically, six control bits allow for an ALU that can perform 2^{6} = 64 functions. The current design supports 18 functions only:

zx | nx | zy | ny | f | no | output function |
---|---|---|---|---|---|---|

1 | 0 | 1 | 0 | 1 | 0 | 0 |

1 | 1 | 1 | 1 | 1 | 1 | 1 |

1 | 1 | 1 | 0 | 1 | 0 | -1 |

0 | 0 | 1 | 1 | 0 | 0 | x |

1 | 1 | 0 | 0 | 0 | 0 | y |

0 | 0 | 1 | 1 | 0 | 1 | !x |

1 | 1 | 0 | 0 | 0 | 1 | !y |

0 | 0 | 1 | 1 | 1 | 1 | -x |

1 | 1 | 0 | 0 | 1 | 1 | -y |

0 | 1 | 1 | 1 | 1 | 1 | x+1 |

1 | 1 | 0 | 1 | 1 | 1 | y+1 |

0 | 0 | 1 | 1 | 1 | 0 | x-1 |

1 | 1 | 0 | 0 | 1 | 0 | y-1 |

0 | 0 | 0 | 0 | 1 | 0 | x+y |

0 | 1 | 0 | 0 | 1 | 1 | x-y |

0 | 0 | 0 | 1 | 1 | 1 | y-x |

0 | 0 | 0 | 0 | 0 | 0 | x AND y (bitwise) |

0 | 1 | 0 | 1 | 0 | 1 | x OR y (bitwise) |

### Design

Multiplexers came in very handy. I was running out of space on the page so the logic for `ng`

and `zr`

is blackboxed in the schematic above.